RISC-V

RISC-V Week will be held from May 3 to 5, 2022 at the Auditorium of the International Conference Center on the Jussieu Campus in Paris.

This new edition is co-organized by CEA, IRT-Nanoelec and RISC-V International: an opportunity to rethink the design of specialized integrated devices and embedded systems in the digital world.

To ensure the sustainability of the digitization of our society, innovation goes in the direction of cost control, reduction of development time but especially energy saving and sobriety.

Developing open hardware and software, creating common bases and solid references, facilitating collaborations… these tracks open the way to frugal innovation.

On the program, a CEA stand and many talks by our experts:

• Tuesday May 3

9h00 – Introductory session

14h00 – “Formal Processor Modeling for Analyzing Safety and Security Properties on RISC-V case studies

• Wednesday May 4th

11:30 am – “VRP/VXP: VaRiable eXtended Precision RISC-V Accelerator for High-Precision

• Thursday, May 5th

A RISC-V International day

For this year, there will also be poster sessions:

• “SCI-FI: Control signal, code and control flow integrity against fault injection attacks”.
• “Formal analysis of the effects of fault injection on RISC-V microarchitecture models”.
• “Pipeline data path models from RISC-V based cores”.
• “An open CAD flow to optimize key gate insertion in logic locking”.

Program and registration here