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Embedded non-volatile memory with robust, optimized accesses

#Computing and distributed systems #Hardware architectures
The CEA has been conducting R&D on resistive memory (ReRAM)— an alternative to flash memory—for more than a decade. A complete system integrating ReRAM into a processor architecture was recently designed and validated for advanced memory company Weebit Nano (Figure 1). Efficiency and energy-delay product gains of 100x and 15x, respectively, were obtained over one million cycles through algorithmic improvements to the calibration of read and write access operations. This research lays the foundation for the next generation of memories Weebit Nano is currently commercializing under license to several foundries.

Israel-based Weebit Nano, founded in 2015, is addressing the memory market with innovative solutions. The company turned to the CEA to develop a complete demonstrator to promote its patented eNVM (embedded non-volatile memory) technology. Weebit Nano has already used the demonstrator to sell or license its technology to foundries in the US and Asia. The CEA’s knowledge of eNVM, circuit and systems design, and wafer- and package-level testing was what originally motivated Weebit Nano to explore the potential for a partnership.

The demonstrator produced includes a non-volatile ReRAM macro and analog circuits that provide the precise, yet tunable signals required for this type of memory’s complex read and write operations (Figure 1). It also includes control circuits based on RISC-V subsystems, as well as a dedicated controller developed specifically for this project.


 

Figure 1

 


The Smart Write Algorithm (SWA) describes how the solution works (Figure 2). Various write-assistance techniques were cleverly implemented to improve the intrinsic characteristics of the ReRAM fabricated at the CEA.

 

Figure 2

 


To achieve this, the system built had to be flexible enough to regulate a large number of current and voltage signals in the ReRAM macro, yet observable enough for detailed characterization. The design techniques used include (Figure 1):

  • Analog techniques limiting or detecting when a threshold current is reached during write operations.
  • Digital techniques, such as:

* Reading the binary value of a memory cell before each write operation and writing only if the bit is not in the desired state.

* Checking the state of the cell after the write operation and repeating the write operation until it is correct.

* An error correction code (ECC) that detects and/or corrects a word read using bits encoding the parity of the word’s subgroups.

This research and, especially, the optimizations obtained by using the Smart Write Algorithm, SWA, led to significant improvements (Figures 2 and main) at room temperature:

  • Functionality: 1 million error-free read and write cycles, 10x better than the current state of the art in ReRAM in the literature.
  • Performance: 83% lower energy consumption and 55% faster access during the write phase compared to implementations with no write-assistance techniques. This corresponds to an 8x reduction in the energy-delay product with ECC (and 15x without).
  • Yield: 100x lower bit error rate (BER) and a 2x read window, positioning the solution well beyond the state of the art both at room temperature and at high temperatures (85 °C).

 

These improvements make the ReRAM technology developed with Weebit Nano a promising candidate for widespread industrial deployment.

This exciting project, which produced the CEA’s first NVM design, involved seven CEA laboratories from technology to circuit design to system-on-chip testing.

Rebecca Cabean

Bastien Giraud

Research Engineer — CEA-List

We are extremely happy with the team’s work... Meeting the schedule for the tapeout, adapting to Weebit change requests, implementing multiple test-modes and flexible design, extremely clean layout.

Ilan Sever

Vice President Research & Development — Weebit Nano LTD.

Key figure

15X

15x improvement in energy-delay product.

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Use cases, applications, technology transfer

  • The ReRAM IP, licensed to the customer, can now be transferred to the customer’s partner foundries (SkyWater, OnSemi, DB HiTek…).

Patents

  • Weebit Nano holds licenses for five patents for the Smart Write Algorithm (SWA), the subject of two publications (JSSC and IMW), and for the error correction codes and signal sequencing during read operations.

Major project and/or partnership

  • This 130 nm design project strengthened the reputation Weebit Nano has built up over many years. It also led to several projects on ECC, security analysis, 22 nm system design, and, coming soon, in-memory computing for AI.

Flagship publications

  • « Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro », B. Giraud et al., in IEEE Journal of Solid-State Circuits, vol. 59, no. 9. https://doi.org/10.1109/JSSC.2024.3386429
  • « Benefits of design assist techniques on performances and reliability of a RRAM macro », B. Giraud et al., IEEE IMW, 2023.