Meet the CEA-List at the RISC-V Summit Europe, from 6 to 9 June 2023 in Barcelona (Spain).
« The RISC-V Summit Europe will be the premier event that connects the European movers and shakers – from industry, government, research, academia and ecosystem support – that are building the future of innovation on RISC-V. »
As a gold sponsor, CEA will be present with a booth. Please come to discuss with our experts and to discover our latest technological innovations:
*VASCO 2: an ASIC demonstrating the latest innovations in component security
VASCO 2 (ASIC Vehicle for component security) integrates innovative patented hardware security bricks on 22nm FD-SOI silicon (processor security, security and acceleration of pre- and post-quantum cryptography, modeling and characterization of random number generators, memory security, etc.). It enables all types of standard or customized tests to be carried out to validate these technologies under operational conditions, with a view to industrial transfer.
*VXP Extended Precision Processor: The « VXP » is an extended precision computing accelerator developed by CEA-List that speeds up scientific computing by a factor typically ranging from 3 to 10 or even more.
For more information : VXP Extended precision Processor (cea.fr)
*VPSim : Explore, simulate, and validate complex electronic architectures
VPSim is a digital architecture design environment used to speed up design space exploration (DSE) through simulation and rapid validation. Users can model a complex memory hierarchy and estimate its performance, for example, thanks to a wide variety of available processor and device models.
For more information : VPSim (cea.fr)
*HybroGen Compilation hybride: The transfer of data between a processor and its memory accounts for 80% of the energy used in computing operations. The downside is that today’s programming languages are not compatible with these innovative architectures. […] The HybroGen compiler represents a break away from 70 years of programming by translating the programmer’s instructions into code that can be executed on these new architectures. The researchers tested HybroGen, using it to program applications on the new architectures.
For more information : July 7, 2021 | In-memory computing could help improve circuit performance (cea.fr)
As a silver sponsor, IRT Nanoelec will be also present with a booth and it will be possible to have information about SCRAMBLE CACHE technology.
More informations on : https://riscv-europe.org/